Many of today's large capacity semiconductor random access memories use multiplexed input address lines in order to limit the number of external pins on the package and to make same compatible with available memories which have smaller capacity. These large capacity memories typically use several sub-arrays which have row and column decoders that must be coupled to the output address lines of an input address buffer. During a typical cycle of operation, row address information is first applied to the input address lines and then after the rows (word lines) of the memory are appropriately selected or deselected, column address information is applied to the input address lines. In some memories, the column decoders receive the row address information and are simultaneously selected or deselected with the row decoders. The column decoders must then be recovered before column address information is applied to the input address lines. This adversely affects access time and increases power dissipation.
It would be desirable in a multiplexed input address memory to have column decoders which are effectively deactivated during the time row address information is being received by the memory and which are fully activated by the subsequent time at which column address information is applied to the memory.